Field effect transistors (FETs) have become the dominant active device for very large scale integration (VLSI) and ultralarge scale integration (ULSI) applications in view of the high impedance, high density and low power characteristics of integrated circuit FETs.
The most common configuration of FET devices is the MOSFET which typically comprises source and drain regions in a semiconductor substrate at a first surface thereof and a gate region therebetween. The gate includes an insulator on the first substrate surface between the source and drain regions, with a gate electrode or contact on the insulator. A channel is present in the semiconductor substrate beneath the gate electrode, and the channel current is controlled by a voltage at the gate electrode.
More recently, in an effort to reduce the channelling during implantation of source/drain dopants in the vertical or depth direction, the substrate has been preamorphized by implanting ions perpendicular to the substrate in the desired locations. This has resulted in shallower junctions in the vertical direction which in turn improves the short channel characteristics of the device. However, as the junction depth has been scaled down to below for example about 30 nanometers, disadvantages occur due to the reduced junction depth. Such disadvantages include increased source/drain resistance (Rsd) and limitation of dopant activation by silicidation. Any advantages achieved by shallow junction formation are offset by these disadvantages.
It would therefore be desirable to achieve improved short channel characteristics such as threshold voltage (Vt) rolloff along with better scalability of MOSFETs and especially CMOS devices in ULSI circuit design without the prior art problems and disadvantages such as increased source/drain resistance.